View MAX6952_1881461.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ________________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the MAX6952 is a compact cathode-row display driver that interfaces microprocessors to 5 ? 7 dot-matrix led displays through an spi-compatible serial interface. the MAX6952 drives up to four digits (140 leds). included on chip are an ascii 104-character font, mul- tiplex scan circuitry, column and row drivers, and static ram that stores each digit, as well as font data for 24 user-definable characters. the segment current for the leds is set by an internal digit-by-digit digital bright- ness control. the device includes a low-power shutdown mode, seg- ment blinking (synchronized across multiple drivers, if desired), and a test mode that forces all leds on. the led drivers are slew rate limited to reduce emi. for a 2-wire interfaced version, refer to the max6953 data sheet. an ev kit is available for the MAX6952. features high-speed 26mhz with spi-/qspi-/ microwire-compatible serial interface 2.7v to 5.5v operation drives four monocolor or two bicolor cathode- row 5 ? 7 matrix displays built-in ascii 104-character font 24 user-definable characters available automatic blinking control for each segment 36? low-power shutdown (data retained) 16-step digital brightness control display blanked on power-up slew-rate-limited segment drivers for lower emi 36-pin ssop and 40-pin dip packages ordering information digit 1 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 digit 0 o0 o1 o2 o3 o4 o5 o6 o14 o15 o16 o17 o18 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 o0 o1 o2 o3 o4 o5 o6 o19 o20 o21 o22 o23 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 r1 r6 r7 c1 r4 r3 r2 r5 c2 c3 c5 c4 digit 3 o7 o8 o9 o10 o11 o12 o13 o19 o20 o21 o22 o23 digit 2 3.3v 100nf 47 f o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 o19 o20 o21 o22 o23 iset osc v+ v+ gnd gnd cs gnd din clk dout c set 26pf r set 53.6k ? MAX6952 blink 3.3v 4.7k ? typical application circuit 19-2437; rev 1; 10/02 evaluation kit available part temp range pin-package MAX6952eax -40 c to +85 c 36 ssop MAX6952epl -40 c to +85 c 40 pdip spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. pin configurations appear at end of data sheet. message boards medical equipment industrial displays audio/video equipment gaming machines applications
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (typical operating circuit, v+ = 3.0v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +6v all other pins................................................-0.3v to (v+ + 0.3v) o0 o13 sink current ....................................................... 500ma o14 o23 source current .................................................. 50ma continuous power dissipation (t a = +70 c) 36-pin ssop (derate 11.8mw/ c above +70 c) .....941.2mw 40-pin pdip (derate 16.7mw/ c above +70 c)........1333mw operating temperature range (t min , t max ) ......-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units operating supply voltage v+ 2.7 5.5 v t a = t min to t max 100 a shutdown supply current i shdn shutdown mode, all digital inputs at v+ or gnd t a = +25 c3680 operating supply current i+ all segments on, intensity set to full, internal oscillator, dout open circuit, no display load connected, blink open circuit 12 16 ma master clock frequency (osc internal oscillator) f osc osc = rc oscillator, r set = 53.6k ? , c set = 26pf 4 mhz master clock frequency (osc external oscillator) f osc osc overdriven externally 1 8 mhz dead clock protection frequency f osc 90 khz osc internal/external detection threshold v osc 1.7 v osc high time t ch 50 ns osc low time t cl 50 ns slow segment blink period (osc internal oscillator) f s l owb l i n k osc = rc oscillator, r set = 53.6k ? , c set = 26pf 1s fast segment blink period (osc internal oscillator) f f a s t b l i n k osc = rc oscillator, r set = 53.6k ? , c set = 26pf 0.5 s fast or slow segment duty cycle (note 2) 49.5 50.5 % column drive source current i column v led = 2.4v, v+ = 3.0v, t a = +25 c -32 -48 ma segment current slew rate ? i seg / ? tt a = +25 o c 12.5 ma/s segment drive current matching (within ic) ? i seg t a = +25 o c4%
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (typical operating circuit, v+ = 3.0v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) note 1: all parameters tested at t a = +25 c. specifications over temperature are guaranteed by design. note 2: guaranteed by design. parameter symbol conditions min typ max units logic inputs and outputs input high voltage din, clk, cs v ih 2.4 v input low voltage din, clk, cs v il 0.4 v input leakage din, clk, cs , osc i ih , i il -2 +0.1 +2 a dout output low voltage v oldo i sink = 1.6ma 0.4 v dout output high voltage v ohdo i source = 1.6ma v+ - 0.4v v blink output low voltage v olbk i sink = 1.6ma 0.4 v timing characteristics (figure 1) clk clock period t cp 38.4 ns clk pulse width high t ch 19 ns clk pulse width low t cl 19 ns cs fall to clk rise setup time t css 9.5 ns clk rise to cs rise hold time t csh 5ns din setup time t ds 9.5 ns din hold time t dh 0ns cs pulse high t csw 19 ns dout propagation delay t do c load = 10pf 19 ns
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 4 _______________________________________________________________________________________ typical operating characteristics (typical application circuit, v+ = 3.3v, led forward voltage = 2.4v, scan limit set to 4 digits, t a = +25 c, unless otherwise noted.) 3.80 3.90 4.10 4.00 4.20 4.30 -40 0 -20 20 40 60 80 internal oscillator frequency vs. temperature MAX6952 toc01 temperature ( c) oscillator frequency (mhz) v+ = 3.3v v+ = 2.7v v+ = 5v internal oscillator frequency vs. supply voltage MAX6952 toc02 supply voltage (v) oscillator frequency (mhz) 4.5 3.5 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 3.6 2.5 5.5 0 0.5 1.5 1.0 2.0 2.5 0 400 200 600 800 internal oscillator waveform at osc MAX6952 toc03 timeline (ns) voltage at osc (v) 80 85 95 90 100 105 2.5 3.5 3.0 4.0 4.5 5.0 5.5 dead clock oscillator frequency vs. supply voltage MAX6952 toc04 supply voltage (v) oscillator frequency (khz) 0.95 0.97 0.96 0.99 0.98 1.00 1.01 2.5 3.5 4.0 3.0 4.5 5.0 5.5 segment source current vs. supply voltage MAX6952 toc05 supply voltage (v) current normalized to 40ma waveforms at o2 (pin 3) and o14 (pin 28) 15/16 intensity ground for anode (pin o14) MAX6952 toc06 ground for cathode (pin o3) 220 m s/div
detailed description the MAX6952 is a serially interfaced display driver that can drive four digits of 5 ? 7 cathode-row dot-matrix displays. the MAX6952 can drive either four monocolor digits (table 1) or two bicolor digits (table 2). the MAX6952 includes a 128-character font map compris- ing 104 predefined characters and 24 user-definable characters. the predefined characters follow the arial font, with the addition of the following common sym- bols: , , , , , , , and . the 24 user-definable characters are uploaded by the user into on-chip ram through the serial interface and are lost when the device is powered down. figure 1 is the MAX6952 functional diagram. serial interface the MAX6952 communicates through an spi-compati- ble 4-wire serial interface. the interface has three inputs, clock (clk), chip select ( cs ), and data in (din), and one output, data out (dout). cs must be low to clock data into or out of the device, and din must be stable when sampled on the rising edge of clk. dout is stable on the rising edge of clk. note that while the spi protocol expects dout to be high impedance when the MAX6952 is not being accessed, dout on the MAX6952 is never high impedance. MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 5 pin description pin ssop pdip name function 1, 2, 3, 6 14, 23, 24 1, 2, 3, 7 15, 26, 27 o0 to o13 led cathode drivers. o0 to o13 outputs sink current from the display s cathode rows. 4, 5, 16 4, 5, 6, 18 gnd ground 15 17 iset segment current setting. connect iset to gnd through series resistor r set to set the peak current. 17 19 blink blink clock output. output is open drain. 18 20 din serial data input. data is loaded into the internal 16-bit shift register on the rising edge of the clk. 19 21 clk serial-clock input. on the rising edge of clk, data is shifted into the internal shift register. on the falling edge of clk, data is clocked out of dout. clk input is active only while cs is low. 20 22 dout serial data output. data clocked into din is output to dout 15.5 clock cycles later. data is clocked out on the rising edge of clk. output is push-pull. 21 23 cs chip-select input. serial data is loaded into the shift register while cs is low. the last 16 bits of serial data are latched on cs s rising edge. 22 24 osc multiplex clock input. to use the internal oscillator, connect capacitor c set from osc to gnd. to use the external clock, drive osc with a 1mhz to 8mhz cmos clock. 25 31, 34, 35, 36 28 34, 38, 39, 40 o14 to o23 led anode drivers. o14 to o23 outputs source current to the display s anode columns. 32, 33 35, 36, 37 v+ positive supply voltage. bypass v+ to gnd with a 47f bulk capacitor and a 0.1f ceramic capacitor.
MAX6952 clk and din may be used to transmit data to other peripherals. the MAX6952 ignores all activity on clk and din except when cs is low. control and operation using the 4-wire interface controlling the MAX6952 requires sending a 16-bit word. the first byte, d15 through d8, is the command byte (table 3), and the second byte, d7 through d0, is the data byte. connecting multiple MAX6952s to the 4-wire bus multiple MAX6952s may be daisy-chained by connect- ing the dout of one device to the din of the next, and driving clk and cs lines in parallel (figure 6). data at din propagates through the internal shift registers and appears at dout 15.5 clock cycles later, clocked out on the falling edge of clk. when sending commands to daisy-chained MAX6952s, all devices are accessed at the same time. an access requires (16 x n) clock cycles, where n is the number of MAX6952s connected together. to update just one device in a daisy-chain, the user can send the no-op command (0x00) to the others. writing device registers the MAX6952 contains a 16-bit shift register into which din data are clocked on the rising edge of sclk, when cs is low. when cs is high, transitions on sclk have no effect. when cs goes high, the 16 bits in the shift 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 6 _______________________________________________________________________________________ digit o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 o19 o20 o21 o22 o23 1 digit 0 rows (cathodes) r1 to r7 digit 1 rows (cathodes) r1 to r7 digit 0 columns (anodes) c1 to c5 digit 1 columns (anodes) c6 to c10 2 digit 2 rows (cathodes) r1 to r7 digit 3 rows (cathodes) r1 to r7 digit 2 columns (anodes) c1 to c5 digit 3 columns (anodes) c6 to c10 table 1. connection scheme for four monocolor digits digit o0 o1 o2 o3 o4 o5 o6 o7 o8 o9 o10 o11 o12 o13 o14 o15 o16 o17 o18 o19 o20 o21 o22 o23 digit 0 columns (anodes) c1 to c10 1 digit 0 rows (cathodes) r1 to r14 - the 5 green anodes - - the 5 red anodes - digit 1 columns (anodes) c1 to c10 2 digit 1 rows (cathodes) r1 to r14 - the 5 green anodes - - the 5 red anodes - table 2. connection scheme for two bicolor digits d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/ w address msb data lsb table 3. serial-data format (16 bits) iset osc blink clk cs din dout serial interface ram blink speed select configuration registers character generator rom character generator ram current source divider/ counter network row multiplexer pwm brightness control led drivers o0 to o23 MAX6952 figure 1. functional diagram
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 7 register are parallel loaded into a 16-bit latch. the 16 bits in the latch are then decoded and executed. the MAX6952 is written to using the following sequence: 1) take clk low. 2) take cs low. this enables the internal 16-bit shift register. 3) clock 16 bits of data into din, d15 first to d0 last, observing the setup and hold times. bit d15 is low, indicating a write command. 4) take cs high (while clk is still high after clocking in the last data bit). 5) take clk low. figure 3 shows a write operation when 16 bits are transmitted. if fewer or greater than 16 bits are clocked into the MAX6952 between taking cs low and taking cs high again, the MAX6952 stores the last 16 bits received, including the previous transmission(s). the general case is when n bits (where n > 16) are transmitted to the MAX6952. the last bits comprising bits {n-15} to {n} are retained and are parallel loaded into the 16-bit latch as bits d15 to d0, respectively (figure 4). reading device registers any register data within the MAX6952 may be read by sending a logic high to bit d15. the sequence is: 1) take clk low. 2) take cs low. this enables the internal 16-bit shift register. 3) clock 16 bits of data into din, d15 first to d0 last, observing the setup and hold times. bit d15 is high, indicating a read command and bits d14 through d8 contain the address of the register to read. bits d7 to d0 contain dummy data, which is discarded. 4) take cs high. positions d7 through d0 in the shift register are now loaded with the data in the register addressed by bits d15 through d8. bits 5) take clk low. 6) issue another read or write command (which can be a no-op), and examine the bit stream at dout; the second 8 bits are the contents of the register addressed by bits d14 through d8 in step 3. digit registers the MAX6952 uses eight digit registers to store the char- acters that the user wishes to display on the four 5 ? 7 led digits. these digit registers are implemented with two planes of 4 bytes, called p0 and p1. each led digit is represented by 2 bytes of memory, 1 byte in plane p0 and the other in plane p1. the digit registers are mapped so that a digit s data can be updated in plane p0, or plane p1, or both planes at the same time (table 4). if the blink function is disabled through the blink enable bit e (table 9) in the configuration register, then the digit register data in plane p0 is used to multiplex the display. the digit register data in p1 is not used. if the blink function is enabled, then the digit register data in both plane p0 and plane p1 are alternately used to mul- tiplex the display. blinking is achieved by multiplexing the led display using data planes p0 and p1 on alter- nate phases of the blink clock (table 10). the data in the digit registers does not control the digit segments directly. instead, the register data is used to address a character generator, which stores the data of a 128-character font (table 14). the lower 7 bits of the digit data (d6 to d0) select the character from the font. the most-significant bit of the register data (d7) selects whether the font data is used directly (d7 = 0) or whether the font data is inverted (d7 = 1). the inversion feature can be used to enhance the appearance of bicolor displays by displaying, for example, a red char- acter on a green background. display blink mode the display blinking facility, when enabled, makes the driver flip automatically between displaying the digit register data in planes p0 and p1. if the digit register data for any digit is different in the two planes, then that digit appears to flip between two characters. to make a character appear to blink on or off, write the character to one plane, and use the blank character (0x20) for the other plane. once blinking has been configured, it con- tinues automatically without further intervention. blink speed the blink speed is determined by frequency of the mul- tiplex clock, osc, and by setting the blink rate selection bit b (table 8) in the configuration register. the blink rate selection bit b sets either fast or slow blink speed for the whole display. initial power-up on initial power-up, all control registers are reset, the display is blanked, intensities are set to minimum, and shutdown is enabled (table 5). configuration register the configuration register is used to enter and exit shutdown, select the blink rate, globally enable and disable the blink function, globally clear the digit data, and reset the blink timing (table 6).
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 8 _______________________________________________________________________________________ t css t cl t ch t cp t csh t csw t ds t dh d15 clk din cs d14 d1 d0 d15 t do dout timing not to scale. figure 2. timing diagram cs clk din d15 = 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dout d15 = 0 figure 3. 16-bit write transmission to the MAX6952 cs clk din bit 1 bit 2 n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1 dout n-15 n-14 n-13 n-12 n-11 n-10 n-9 n n-15 n-31 n-30 n-29 n-28 n-27 n-26 n-25 n-24 n-23 n-22 n-21 n-20 n-19 n-18 n-17 n-16 timing not to scale. figure 4. transmission of more than 16 bits to the MAX6952
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver _______________________________________________________________________________________ 9 address (command byte) register d15 d14 d13 d12 d11 d10 d9 d8 hex code no-op r/ w 0000000 0x00 intensity10 r/ w 0000001 0x01 intensity32 r/ w 0000010 0x02 scan-limit r/ w 0000011 0x03 configuration r/ w 0000100 0x04 user-defined fonts r/ w 0000101 0x05 factory reserved. do not write to this. r/ w 0000110 0x06 display test r/ w 0000111 0x07 digit 0 plane p0 r/ w 0100000 0x20 digit 1 plane p0 r/ w 0100001 0x21 digit 2 plane p0 r/ w 0100010 0x22 digit 3 plane p0 r/ w 0100011 0x23 digit 0 plane p1 r/ w 1000000 0x40 digit 1 plane p1 r/ w 1000001 0x41 digit 2 plane p1 r/ w 1000010 0x42 digit 3 plane p1 r/ w 1000011 0x43 write digit 0 plane p0 and plane p1 with same data (reads as 0x00) r/ w 1100000 0x60 write digit 1 plane p0 and plane p1 with same data (reads as 0x00) r/ w 1100001 0x61 write digit 2 plane p0 and plane p1 with same data (reads as 0x00) r/ w 1100010 0x62 write digit 3 plane p0 and plane p1 with same data (reads as 0x00) r/ w 1100011 0x63 table 4. register address map
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 10 ______________________________________________________________________________________ shutdown mode (s data bit d0) format the s bit in the configuration register selects shutdown or normal operation (table 7). the display driver can be programmed while in shutdown mode, and shutdown mode is overridden when in display test mode. for nor- mal operation, the s bit should be set to 1. blink rate selection (b data bit d2) format the b bit in the configuration register selects the blink rate. this is the speed that the segments alternate between plane p0 and plane p1 refresh data. the blink rate is determined by the frequency of the multiplex clock osc, in addition to the setting of the b bit (table 8). global blink enable/disable (e data bit d3) format the e bit globally enables or disables the blink feature of the device (table 9). when blink is globally enabled, then the digit data in both planes p0 and p1 are used to control the display (table 10). register data register power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 intensity10 1/16 (min on) 0x01 00000000 intensity32 1/16 (min on) 0x02 00000000 scan limit display 4 digits: 0 1 2 3 0x03 xxxxxxx1 configuration shutdown enabled, blink speed is slow, blink disabled 0x04 0 x 0000x0 user-defined font address pointer address 0x80; pointing to the first user-defined font location 0x05 10000000 display test normal operation 0x07 xxxxxxx0 digit 0 plane p0 blank digit (0x20) 0x20 00100000 digit 1 plane p0 blank digit (0x20) 0x21 00100000 digit 2 plane p0 blank digit (0x20) 0x22 00100000 digit 3 plane p0 blank digit (0x20) 0x23 00100000 digit 0 plane p1 blank digit (0x20) 0x40 00100000 digit 1 plane p1 blank digit (0x20) 0x41 00100000 digit 2 plane p1 blank digit (0x20) 0x42 00100000 digit 3 plane p1 blank digit (0x20) 0x43 00100000 table 5. initial power-up register status register data register d7 d6 d5 d4 d3 d2 d1 d0 configuration register pxrtebxs table 6. configuration register format register data mode d7 d6 d5 d4 d3 d2 d1 d0 shutdown mode pxrtebx0 normal operation pxrtebx1 table 7. shutdown control (s data bit d0) format
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 11 MAX6952 dout microcontroller clk din MAX6952 MAX6952 clk din cs dout clk din cs dout clk din cs dout cs figure 6. MAX6952 daisy-chain connection register data mode d7 d6 d5 d4 d3 d2 d1 d0 slow blinking (segments are refreshed using plane p0 for 1s, plane p1 for 1s, for osc = 4mhz. ) pxrte0xs table 8. blink rate selection (b data bit d2) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 blink function is disabled. p x r t 0 b x s blink function is enabled. p x r t 1 b x s table 9. global blink enable/disable (e data bit d3) format when blink is globally disabled, then only the digit data in plane p0 is used to control the display. the digit data in plane p1 is ignored. global blink timing synchronization (t data bit d4) format by setting the t bit in multiple MAX6952s at the same time (or in quick succession), the blink timing can be synchronized across all the devices (table 11). note that the display multiplexing sequence is also reset, which might give rise to a one-time display flicker when the register is written. global clear digit data (r data bit d5) format when global digit data clear is set, the digit data for both planes p0 and p1 for all digits is cleared (table 12). blink phase readback (p data bit d7) format when the configuration register is read, the p bit reflects the state of the blink output pin at that time (table 13). character generator font mapping the font is a 5 ? 7 matrix comprising 104 characters in rom, and 24 user-definable characters. the selection from the total of 128 characters is represented by the lower 7 bits of the 8-bit digit registers. the most-signifi- cant bit, shown as x in the rom map below, is zero to light leds as shown by the black segments in table 14, and 1 to display the inverse. the character map follows the arial font for 96 charac- ters in the x0101000 through x1111111 range. the first
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 12 ______________________________________________________________________________________ 32 characters map the 24 user-definable positions (ram00 to ram23), plus eight extra common charac- ters in rom. user-defined fonts the 24 user-definable characters are represented by 120 entries of 7-bit data, five entries per character, and are stored in the MAX6952's internal ram. the 120 user-definable font data entries are written and read through a single register, address 0x05. an autoincrementing font address pointer in the MAX6952 indirectly accesses the font data. the font address pointer can be written, setting one of 120 addresses between 0x00 and 0xf7, but cannot be read back. the font data is written to and read from the MAX6952 indi- rectly, using this font address pointer. unused font locations can be used as general-purpose scratch ram, bearing in mind that the font registers are only 7 bits wide, not 8. table 15 shows how the single user-defined font regis- ter 0x05 is used to set the font address pointer, write font data, and read font data. a read action always returns font data from the font address pointer position. a write action sets the 7-bit font address pointer if the msb is set, or writes 7-bit font data to the font address pointer position if the msb is clear. the font address pointer autoincrements after a valid access to the user-definable font data. auto- incrementing allows the 120 font data entries to be writ- ten and read back very quickly because the font point- er address need only be set once. when the last data location 0xf7 is written, the font address pointer autoin- crements to address 0x80. if the font address pointer is set to an out-of-range address by writing data in the 0xf8 to 0xff range, then address 0x80 is set instead (table 16). table 17 shows the user-definable font pointer base addresses. segment s bit setting in plane p1 segment s bit setting in plane p0 segment behavior 0 0 segment off 01 segment on only during the 1st half of each blink period 10 segment on only during the 2nd half of each blink period 1 1 segment on table 10. digit register mapping with blink globally enabled register data mode d7 d6 d5 d4 d3 d2 d1 d0 blink timing counters are unaffected. p x r 0 e b x s blink timing counters are reset on the rising edge of cs .pxr1ebxs table 11. global blink timing synchronization (t data bit d4) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 digit data for both planes p0 and p1 are unaffected. p x 0 t e b x s digit data for both planes p0 and p1 are cleared on the rising edge of cs . px1tebxs table 12. global clear digit data (r data bit d5) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 p1 blink phase 0 x r t e b x s p0 blink phase 1 x r t e b x s table 13. blink phase readback (p data bit d7) format
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 13 table 18 shows an example of data (characters 0, 1, and 2) being stored in the first three user-defined font locations, illustrating the orientation of the data bits. table 19 shows the six sequential write commands required to set a max6953's font character ram02 with the data to display character 2 given in the font ram illustration above. multiplex clock and blink timing the osc pin can be fitted with capacitor c set to gnd (to use the internal rc multiplex oscillator), or driven by an external clock. the multiplex clock frequency deter- mines the multiplex scan rate and the blink timing. the display scan rate is calculated by dividing the frequency at osc by 5600. with osc at 4 mhz, each display digit is enabled for 100s and the display scan rate is 714.29hz. the on-chip oscillator may be accurate enough for applications using a single device. if an exact blink rate is required, use an external clock ranging between 1mhz and 8mhz to drive osc. the osc inputs of multi- ple MAX6952s can be tied together to a common exter- nal clock to make the devices blink at the same rate. the relative blink phasing of multiple MAX6952s can be synchronized by setting the t bit in the control register for all the devices in quick succession (table 11). if the serial interfaces of multiple MAX6952s are daisy- chained by connecting dout of one device to din of the next, then synchronization is achieved automatically by updating the control register for all devices together. for MAX6952s, the devices can be synchronized by transmitting the serial data for the control register, and then toggling the cs pin for each device, either togeth- er or in quick succession. figure 7 is the multiplex tim- ing diagram. blink output the blink output indicates the blink phase, and is high during the p0 period and low during the p1 period. blink phase status can also be read back as the p bit in the configuration register (table 13). typical uses for this output are: to provide an interrupt to the processor so that seg- ment data can be changed synchronous to the blinking. for example, a clock application may have colon segments blinking every second between hours and minute digits, and the minute display is best changed in step with the colon segments. also, if the rising edge of blink is detected, there is half a blink period to change the p1 digit data. similarly, if the falling edge of blink is detected, the user has half a blink period to change the p0 digit data. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 x000 x001 x010 x011 x100 x101 x110 x111 ram00 ram01 ram02 ram03 ram04 ram05 ram06 ram07 msb lsb ram08 ram09 ram10 ram11 ram12 ram13 ram14 ram15 ram16 ram17 ram18 ram19 ram20 ram21 ram22 ram23 table 14. character map
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 14 ______________________________________________________________________________________ if osc is driven with an accurate frequency, blink can be used as a seconds counter or similar. scan-limit register the scan-limit register sets how many monocolor digits are displayed, either two or four. a bicolor digit is con- nected as two monocolor digits. the multiplexing scheme drives digits 0 and 1 at the same time, then digits 2 and 3 at the same time. to increase the effective brightness of the displays, drive only two digits instead of four. by doing this, the aver- age segment current doubles, but also doubles the number of MAX6952s required to drive a given number of digits. because digit 1 is driven at the same time as digit 0 (and digit 3 is driven at the same time as digit 2), only 1 bit is used to set the scan limit. the bit is clear if one or two digits are to be driven, and set if three or four digits are to be driven (table 20). change the scan-limit register only when the MAX6952 is in shutdown mode. intensity registers display brightness is controlled digitally by four pulse- width modulators, one for each display digit. each digit is controlled by a nibble of one of the two intensity registers, intensity10 and intensity32. the modulator scales the average segment current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current. the minimum interdigit blanking time is, therefore, 1/16 of a cycle. the maximum duty cycle is 15/16. (tables 21 and 22). no-op register a write to the no-op register is ignored. selecting external components r set and c set to set oscillator frequency and segment current the rc oscillator uses an external resistor rset and an external capacitor c set to set the oscillator frequency, f osc . the allowed range of f osc is 1mhz to 8mhz. r set also sets the peak segment current. the recom- mended values of r set and c set set the oscillator to 4mhz, which makes the blink frequencies 0.5hz and 1hz. the recommended value of r set also sets the peak current to 40ma, which makes the segment cur- rent adjustable from 2.5ma to 37.5ma in 2.5ma steps: i seg = k i / r set ma f osc = k f / (r set ? c set + c stray ) mhz where: k i = 2144 k f = 6000 r set = external resistor in k ? c set = external capacitor in pf c stray = stray capacitance from osc pin to gnd in pf, typically 2pf the recommended value of r set is 53.6k ? and the recommended value of c set is 26pf. address code (hex) register data spi read or write function 0x85 0x00 0x7f read read 7-bit user-definable font data entry from current font address. msb of the register data is clear. font address pointer is incremented after the read. 0x05 0x00 0x7f write write 7-bit user-definable font data entry to current font address. font address pointer is incremented after the write. 0x05 0x80 0xff write write font address pointer with the register data. table 15. memory mapping of user-defined font register 0x05 font pointer address action 0x80 to 0xf6 valid range to set the font address pointer. pointer autoincrements after a font data read or write, while pointer address remains in this range. 0xf7 font address resets to 0x80 after a font data read or write to this pointer address. 0xf8 to 0xff invalid range to set the font address pointer. pointer is set to 0x80 if address. table 16. font pointer address behavior
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 15 register data font character address code (hex) register data (hex) d7 d6 d5 d4 d3 d2 d1 d0 ram00 0x05 0x80 1 0 0 0 0 0 0 0 ram01 0x05 0x85 1 0 0 0 0 1 0 1 ram02 0x05 0x8a 1 0 0 0 1 0 1 0 ram03 0x05 0x8f 1 0 0 0 1 1 1 1 ram04 0x05 0x94 1 0 0 1 0 1 0 0 ram05 0x05 0x99 1 0 0 1 1 0 0 1 ram06 0x05 0x9e 1 0 0 1 1 1 1 0 ram07 0x05 0xa3 1 0 1 0 0 0 1 1 ram08 0x05 0xa8 1 0 1 0 1 0 0 0 ram09 0x05 0xad 1 0 1 0 1 1 0 1 ram10 0x05 0xb2 1 0 1 1 0 0 1 0 ram11 0x05 0xb7 1 0 1 1 0 1 1 1 ram12 0x05 0xbc 1 0 1 1 1 1 0 0 ram13 0x05 0xc1 1 1 0 0 0 0 0 1 ram14 0x05 0xc6 1 1 0 0 0 1 1 0 ram15 0x05 0xcb 1 1 0 0 1 0 1 1 ram16 0x05 0xd0 1 1 0 1 0 0 0 0 ram17 0x05 0xd5 1 1 0 1 0 1 0 1 ram18 0x05 0xda 1 1 0 1 1 0 1 0 ram19 0x05 0xdf 1 1 0 1 1 1 1 1 ram20 0x05 0xe4 1 1 1 0 0 1 0 0 ram21 0x05 0xe9 1 1 1 0 1 0 0 1 ram22 0x05 0xee 1 1 1 0 1 1 1 0 ram23 0x05 0xf3 1 1 1 1 0 0 1 1 table 17. user-definable font pointer base address table the recommended value of r set is the minimum allowed value since it sets the display driver to the maximum allowed segment current. r set can be set to a higher value to set the segment current to a lower peak value where desired. the user must also ensure that the peak current specifications of the leds con- nected to the driver are not exceeded. the effective value of c set includes not only the actual external capacitor used, but also the stray capacitance from osc to gnd. this capacitance is usually in the 1pf to 5pf range, depending on the layout used. display-test register the display-test register switches the drivers between one of two modes: normal and display test. display-test mode turns all leds on by overriding, but not altering, all control and digit registers (including the shutdown register). in display-test mode, eight digits are scanned and the duty cycle is 7/16 (half power). table 23 lists the display-test register format. applications information choosing supply voltage to minimize power dissipation the MAX6952 drives a peak current of 40ma into leds with a 2.4v forward-voltage drop when operated from a supply voltage of at least 3.0v. the minimum voltage drop across the internal led drivers is, therefore (3.0v - 2.4v) = 0.6v. if a higher supply voltage is used, the dri- ver absorbs a higher voltage, and the driver s power dissipation increases accordingly. however, if the leds used have a higher forward voltage drop than 2.4v, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.6v headroom.
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 16 ______________________________________________________________________________________ register data font character font address pointer address code (hex) font pointer address (hex) d7 d6 d5 d4 d3 d2 d1 d0 ram00 0x00 0x05 0x80 0 0 1 1 1 1 1 0 ram00 0x01 0x05 0x81 0 1 0 1 000 1 ram00 0x02 0x05 0x82 0 1 00 1 00 1 ram00 0x03 0x05 0x83 0 1 000 1 0 1 ram00 0x04 0x05 0x84 0 0 1 1 1 1 1 0 ram01 0x05 0x05 0x85 0 0 0 0 0 0 0 0 ram01 0x06 0x05 0x86 0 1 0000 1 0 ram01 0x07 0x05 0x87 0 1 1 1 1 1 1 1 ram01 0x08 0x05 0x88 0 1 000000 ram01 0x09 0x05 0x89 0 0 0 0 0 0 0 0 ram02 0x0a 0x05 0x8a 0 1 0000 1 0 ram02 0x0b 0x05 0x8b 0 1 1 0000 1 ram02 0x0c 0x05 0x8c 0 1 0 1 000 1 ram02 0x0d 0x05 0x8d 0 1 00 1 00 1 ram02 0x0e 0x05 0x8e 0 1 000 1 1 0 table 18. user-definable character storage example address code (hex) register data (hex) action being performed 0x05 0x8a set font address pointer to the base address of font character ram02. 0x05 0x42 1st 7 bits of data: 1000010 goes to font address 0x8a; pointer then autoincrements to address 0x8b. 0x05 0x61 2nd 7 bits of data: 1100001 goes to font address 0x8b; pointer then autoincrements to address 0x8c. 0x05 0x51 3rd 7 bits of data: 1010001 goes to font address 0x8c; pointer then autoincrements to address 0x8d. 0x05 0x49 4th 7 bits of data: 1001001 goes to font address 0x8d; pointer then autoincrements to address 0x8e. 0x05 0x46 5th 7 bits of data: 1000110 goes to font address 0x8e; pointer then autoincrements to address 0x8f. table 19. setting a font character to ram example register data scan limit address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 hex code display digits 0 and 1 only 0x03 x x x xxxx0 0xx0 display digits 0, 1, 2, and 3 0x03 x x x xxxx1 0xx1 table 20. scan limit register format
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 17 duty cycle typical segment current (ma) address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 hex code 1/16 (min on) 2.5 0x01, 0x02 0000 0xx0 2/16 5 0x01, 0x02 0001 0xx1 3/16 7.5 0x01, 0x02 0010 0xx2 4/16 10 0x01, 0x02 0011 0xx3 5/16 12.5 0x01, 0x02 0100 0xx4 6/16 15 0x01, 0x02 0101 0xx5 7/16 17.5 0x01, 0x02 see table 22. 0110 0xx6 8/16 20 0x01, 0x02 0111 0xx7 9/16 22.5 0x01, 0x02 1000 0xx8 10/16 25 0x01, 0x02 1001 0xx9 11/16 27.5 0x01, 0x02 1010 0xxa 12/16 30 0x01, 0x02 1011 0xxb 13/16 32.5 0x01, 0x02 1100 0xxc 14/16 35 0x01, 0x02 1101 0xxd 15/16 37.5 0x01, 0x02 1110 0xxe 15/16 (max on) 37.5 0x01, 0x02 1111 0xxf table 21. intensity register format for digit 0 (address 0x01) and digit 2 (address 0x02) duty cycle typical segment current (ma) address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 hex code 1/16 (min on) 2.5 0x01, 0x02 0000 0x0x 2/16 5 0x01, 0x02 0001 0x1x 3/16 7.5 0x01, 0x02 0010 0x2x 4/16 10 0x01, 0x02 0011 0x3x 5/16 12.5 0x01, 0x02 0100 0x4x 6/16 15 0x01, 0x02 0101 0x5x 7/16 17.5 0x01, 0x02 0110 0x6x 8/16 20 0x01, 0x02 0111 see table 21. 0x7x 9/16 22.5 0x01, 0x02 1000 0x8x 10/16 25 0x01, 0x02 1001 0x9x 11/16 27.5 0x01, 0x02 1010 0xax 12/16 30 0x01, 0x02 1011 0xbx 13/16 32.5 0x01, 0x02 1100 0xcx 14/16 35 0x01, 0x02 1101 0xdx 15/16 37.5 0x01, 0x02 1110 0xex 15/16 (max on) 37.5 0x01, 0x02 1111 0xfx table 22. intensity register format for digit 1 (address 0x01) and digit 3 (address 0x02)
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 18 ______________________________________________________________________________________ register data mode address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 normal operation 0x07 xxxxxxx0 display test 0x07 xxxxxxx1 table 23. display-test register format the voltage drop across the drivers with a nominal 5v supply (5.0v - 2.4v) = 2.6v is nearly 3 times the drop across the drivers with a nominal 3.3v supply (3.3v - 2.4v) = 0.9v. in most systems, consumption is an important design criterion, and the MAX6952 should be operated from the system s 3.3v nominal supply. in other designs, the lowest supply voltage may be 5v. the issue now is to ensure the dissipation limit for the MAX6952 is not exceeded. this can be achieved by inserting a series resistor in the supply to the MAX6952, ensuring that the supply decoupling capacitors are still on the MAX6952 side of the resistor. for example, con- sider the requirement that the minimum supply voltage to a MAX6952 must be 3.0v, and the input supply range is 5v 5%. maximum supply current is: 12ma + (40ma x 10) = 412ma minimum input supply voltage is 4.75v. maximum series resistor value is: (4.75v - 3.0v) / 0.412a = 4.25 ? we choose 3.3 ? 5%. worst-case resistor dissipation is at maximum toleranced resistance, i.e., (0.412a) 2 x (3.3 ? ? 1.05) = 0.577w. we choose a 1w resistor rat- ing. the maximum MAX6952 supply voltage is at maxi- mum input supply voltage and minimum toleranced resistance, i.e., 5.25v - (0.412a x 3.3 ? ? 0.95) = 3.97v. low-voltage operation the MAX6952 works over the 2.7v to 5.5v supply range. the minimum useful supply voltage is deter- mined by the forward voltage drop of the leds at the peak current i seg , plus the 0.6v headroom required by the driver output stages. the MAX6952 correctly regu- lates i seg with a supply voltage above this minimum voltage. if the supply drops below this minimum volt- age, the driver output stages may brown out, and be unable to regulate the current correctly. as the supply voltage drops further, the led segment drive current becomes effectively limited by the output driver's on- resistance, and the led drive current drops. the char- acteristics of each individual led in a 5 ? 7 matrix digit are well matched, so the result is that the display inten- sity dims uniformly as supply voltage drops out of regu- lation and beyond. the MAX6952 operates down to 2.5v supply voltage (although most displays are very dim at this voltage), provided that the MAX6952 is pow- ered up initially to at least 2.7v to trigger the device's internal reset. computing power dissipation the upper limit for power dissipation (pd) for the MAX6952 is determined from the following equation: p d = (v+ ? 12ma) + (v+ - v led ) (duty x i seg ? n) where: v+ = supply voltage duty = duty cycle set by intensity register n = number of segments driven (worst case is 10) v led = led forward voltage i seg = segment current set by r set p d = power dissipation, in mw if currents are in ma dissipation example: i seg = 40ma, n = 10, duty = 15 / 16, v led = 2.4v at 40ma, v+ = 3.6v p d = 3.6v (12ma) + (3.6v - 2.4v)(15 / 16 ? 40ma ? 10) = 0.493w thus, for a 36-pin ssop package (t ja = 1 / 0.0118 = +85 c/w from operating ratings), the maximum allowed ambient temperature t a is given by: t j(max) = t a + (p d ? t ja ) = +150 c = t a + (0.493 ? +85 c/w) so, t a = +108 c. thus, the part can be operated safely at a maximum package temperature of +85 c. power supplies the MAX6952 operates from a single 2.7v to 5.5v power supply. bypass the power supply to gnd with a 0.1f capacitor as close to the device as possible. add a 47f capacitor if the MAX6952 is not close to the board s input bulk decoupling capacitor.
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver ______________________________________________________________________________________ 19 digit 1 row 1 digit 1 row 2 digit 1 row 3 digit 1 row 4 digit 1 row 5 digit 1 row 6 digit 1 row 7 digit 3 row 1 digit 3 row 2 digit 3 row 3 digit 3 row 4 digit 3 row 5 digit 3 row 6 digit 3 row 7 digit 1 row 1 column driver pins o19-o23 digit 0 row 1 digit 0 row 2 digit 0 row 3 digit 0 row 4 digit 0 row 5 digit 0 row 6 digit 0 row 7 digit 2 row 1 digit 2 row 2 digit 2 row 3 digit 2 row 4 digit 2 row 5 digit 2 row 6 digit 2 row 7 digit 0 row 1 column driver pins o14-o18 digit 1 row 1? 100 s multiplex timeslot current source 1/16th 2/16th (min on) 3/16th 4/16th 5/16th 6/16th 7/16th 8/16th 9/16th 10/16th 11/16th 12/16th 13/16th 14/16th 15/16th 16/16th (max on) current source current source current source current source current source current source current source current source current source current source current source current source current source current source current source one complete 1.4ms multiplex cycle around 14 rows 100 s digit 1 column driver outputs pins o19-o23 high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z digits 0 & 1 row outputs pins o0?6 high-z low digits 2 & 3 row outputs pins o7?13 high-z high-z high-z minimum 6.25 s interdigit blanking interval start of next cycle figure 7. multiplex timing diagram (osc = 4mhz)
pin configurations 40 o23 o22 o21 v+ v+ v+ o20 o19 o18 o17 o16 o15 o14 o13 o12 n.c. osc dout clk 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 o0 o1 o2 gnd gnd gnd o3 o4 o5 o6 o7 o8 o9 o10 o11 n.c. iset gnd blink din top view MAX6952 30 29 28 27 26 25 24 23 22 21 11 12 13 14 15 16 17 18 19 pdip 20 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 o23 o22 o21 v+ v+ o20 o12 o19 o18 o17 o16 o15 o14 o13 o11 o10 o9 o8 o7 o6 o5 o4 o3 gnd gnd o2 o1 o0 ssop MAX6952 22 21 20 19 15 16 17 18 clk osc dout din blink gnd iset cs cs MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver 20 ______________________________________________________________________________________ board layout when designing a board, use the following guidelines: 1) the r set connection to the iset pin is a high-imped- ance node, and sensitive to layout. place r set right next to the iset pin and route r set directly to these pins with very short tracks. 2) ensure that the track from the ground end of r set routes directly to gnd pin 18 (pdip package) or gnd pin 16 (ssop package), and that this track is not used as part of any other ground connection. chip information transistor count: 43,086 process: cmos
MAX6952 4-wire interfaced, 2.7v to 5.5v, 4-digit 5 ? 7 matrix led display driver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 21 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. ssop.eps package outline, 36l ssop, 0.80 mm pitch 1 1 21-0040 e rev. document control no. approval proprietary information title: front view max 0.011 0.104 0.017 0.299 0.013 inches 0.291 0.009 e c dim 0.012 0.004 b a1 min 0.096 a 0.23 7.40 7.60 0.32 millimeters 0.10 0.30 2.44 min 0.44 0.29 max 2.65 0.040 0.020 l 0.51 1.02 h 0.414 0.398 10.11 10.51 e 0.0315 bsc 0.80 bsc d 0.612 0.598 15.20 15.55 h e a1 a d e b 0-8 l c top view side view 1 36 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

▲Up To Search▲

Price & Availability of MAX6952

	To Download MAX6952 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .